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7th IEEE International Workshop on Silicon Debug and Diagnosis
(SDD 2011)

September 22-23, 2011
Anaheim, California, USA

http://www.sdd-online.org

Immediately following the 2011 International Test Conference

CALL FOR PARTICIPATION

Scope -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

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Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work is however very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market. New and efficient solutions for debug and diagnosis have a much needed and highly visible impact on productivity.

SDD 2011 will be held in Anaheim, California, USA.   It is the seventh of a series of highly successful technical workshops that consider issues related to debug & diagnosis of semiconductor circuits and systems - from prototype bring-up to volume production. 

Workshop Registration
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Workshop Registration

Advance Program
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Thursday -- Friday

September 22, 2011 (Thursday)
 
4:00 PM - 6:00 PM OPENING SESSION
4:00 - 4:15

Opening Remarks
T. McLaurin, ARM, I. Hartanto, Xilinx

4:15 - 5:00

Keynote Address

5:00 - 5:30
Invited Address
6:00 - 7:00
Experience & Opinion
 
7:00 PM - 9:00 PM WORKSHOP WELCOME RECEPTION
 
September 23, 2011 (Friday)
 
8:00 AM - 10:00 AM Session 1
 

Paper 1 – Understanding ATE capabilities to leverage during silicon debug
N. Dakwala, Broadcom

 

Paper 2 – Efficient Post-Silicon Verification and Debugging with Patchable/Programmable Accelerators Synthesized from High Level Designs
M. Fujita, Univ. of Tokyo

 

Paper 3 – Extending Constrained Random Verification to mixed-signal Automotive Power Devices using a non-stationary Markov Process
T. Nirmaier, M. Harrant, G. Pelz, Infineon AG

  Paper 4 – Integrating Debug Hardware with Digital Tester to Enable Functional Pattern Execution without Vector Generation for Power and Performance Benchmarking
C. Hawkins, ARM
 
10:30 AM - 12:00 PM Session 2
 

Paper 5 – Exploring CΔIDDQ Bridging Defect Diagnosis Capabilities
C. Thibeault, Y. Hariri, H. Khaled, Ecole de Technologie superieure

  Paper 6 – New Approaches for Analysis of Logic Fail Data
R. Dokken, V, Tancorre, ST Micro
  Paper 7 – Failing within Passing Region
S. Kumar, Broadcom
 
12:00 PM - 1:30 PM LUNCH
 
1:30 PM - 2:45 PM Session 3 - Panel Discussion: Digital test is a solved problem! The future must focus on post-silicon validation and debug
Chair: E. Rentschler, AMD
 
3:00 PM - 4:00 PM Session 4
 

Paper 8 – Yield, Reliability, Lasers, and Shift Defect Isolation
S. Kasapi, J. Liao, NVIDIA

 

Paper 9 – Evolution of CAD for Silicon Debug: from the IDM FA Lab to the Fabless and Foundry Yield Collaboration
C. Kardach, H. Suri, J. Gade, DCG Systems

 
More Information
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For general information contact:
General Chair: Teresa McLaurin
Teresa.McLaurin@arm.com

For program information contact:
Program Chair: Ismed Hartanto
Ismed.Hartanto@xilinx.com

Committees
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General Chair
T. McLaurin - ARM

Program Chair
I. Hartanto – Xilinx

Special Sessions
E. Rentschler - AMD

Asian Liaison
K. Hatayama - NAIST

European Liaison
D. Appello - STMicroelectroincs

Electronic Media
I. Bayraktaroglu - Oracle  

Program Committee
B. Benware – Mentor Graphics
C. Boit – TU Berlin
B. Cory – nVidia
A. Crouch – ASSET Intertech
B. Eklow – Cisco Systems
R. Guo – Mentor Graphics
S. Gupta - USC
Y-C. Hsu – SpringSoft
D. Josephson – Intel
R. Kapur – Synopsys
C. Metra – U. Bologna
A. Orailoglu – UCSD
S. Pappalardo - STMicroelectronics
P. Prinetto – Poli. Di Torino
M. Renovell – LIRMM
M.S. Reorda – Poli. Di Torino
C. Sul – Silicon Image
J. Tyzer – U. Poznan
S. Venkataraman – Intel
Q. Xu – Chinese Univ. of Hong Kong
Z. Zilic – McGill Univ.

Steering Committee:
R. Aitken - ARM
E. J. Marinissen – IMEC
F. Muradali – National Semiconductor
M. Ricchetti  (Chair) – AMD
B. Vermeulen – NXP
Y. Zorian - Synopsys

For more information, visit us on the web at: http://www.sdd-online.org

The 7th IEEE International Workshop on Silicon Debug and Diagnosis (SDD 2011 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Joan FIGUERAS
UPC Barcelona Tech - Spain
Tel. +
E-mail figueras@eel.upc.edu

ITC GENERAL CHAIR
Doug YOUNG
- USA
Tel. +1-602-617-0393
E-mail doug0037@aol.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Athens
- Greece
Tel. +30-210-7275145
E-mail dgizop@di.uoa.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1-
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM – France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel. +81 743 72 5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com